1. Field of the Invention
The present invention relates to the electronics field. More specifically, the present invention relates to EEPROM memories.
2. Discussion of the Related Art
Memories are commonly used in several applications for storing information temporarily, in the so-called volatile memories, or permanently, in the so-called non-volatile memories, which are able to preserve the information also in absence of power supply. A particular type of non-volatile memories consists of the EEPROM (“Electrically Erasable Programmable Read Only Memory”) type.
An EEPROM memory comprises a matrix of cells, which can be electrically programmed and erased. Each memory cell is formed by a memory element (such as a floating gate MOS transistor) in series to a selection MOS transistor. The programming and erasing operations on the memory cell are assisted by the known Fowler-Nordheim mechanism, which causes the passage of charge (electrons) by tunnel effect from and to the floating gate of the floating gate MOS transistor. In such a way, the memory cell stores a logic value defined by the threshold voltage of the floating gate MOS transistor, which depends on the electric charge stored on the gate thereof. The selection transistor is used for accessing the floating gate MOS transistor and in particular for biasing it by suitable biasing voltages so as to perform the desired operation. In detail, in order to store (positive or negative) charge on the floating gate of the floating gate MOS transistor—and thus obtain significant Fowler-Nordheim currents (for example, 60 pA/cell)—it is needed to apply high programming or erasing voltages, denoted as a whole as writing voltages (for example, 12V-13V) to the memory cell.
The memory cells are arranged in the matrix in rows and columns. In particular, the memory cells arranged on a same row are grouped in one or more words and are connected to a common word line, whereas the memory cells arranged on a same column are connected to a common bit line.
For retrieving or storing the information, the memory comprises a decoding system, which is adapted to decode an input address identifying one or more memory cells. In particular, the decoding system comprises a row decoder for selecting a word line and a column decoder for selecting one or more bit lines. Such decoders receive low voltage input logic signals (that is of the order of a power supply of the memory—for example 1.65V), but have to be able to apply the high writing voltages required during the erasing and programming operations to the word line and to the selected bit lines—which writing voltages are higher than the power supply of the memory and are usually generated by means of suitable circuits (for example, charge pumps) provided within the memory.
Thus, such biasing circuits have to include high voltage electronic components, which are able to sustain (between the terminals thereof) voltage differences at least equal to the writing voltage. For example, these components can be high voltage MOS transistors, which are designed in such a way to avoid the breaking of the gate oxide or the breakdown of the junctions when voltage differences equal or higher than the writing voltages are applied between the terminals thereof.
The high voltage MOS transistors have a sufficiently thick gate oxide (of the order of 15 nm) since the voltage differences sustained between the terminals thereof are higher as the gate oxide is thicker. For this reason, the high voltage MOS transistors and thus also the biasing circuits occupy a significant area of a semiconductor material chip wherein the EEPROM memory is integrated.
Moreover, since typically the EEPROM memories provide a biasing circuit for each bit line, this problem is more evident as the number of the bit lines increases.
Another problem of the EEPROM memory is to ensure that the memory cells are correctly written. Indeed, when one or more memory cells of the EEPROM memory are programmed, it can happen that, because of leakage phenomena, the information stored in the remaining memory cells (that is those which are not to be programmed) is changed. Indeed, such leakage phenomena cause an undesired emptying of the floating gates of the floating gate MOS transistors of the non-selected memory cells, so that the corresponding threshold voltage takes values different from the expected ones. For avoiding such inconvenience, the known solutions provide the use of decoding systems wherein the transistors used for providing the writing voltages to the bit lines are n-channel MOS transistors (since the leakage phenomena are lower with respect to those of n-channel type). However, because of the body effect, such transistors have to be able to sustain voltages even higher than the writing voltages between the terminals thereof; this further increases the area occupied on the semiconductor material chip.